Thermal Stress and Strain in Microelectronics Packaging

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Factors that must be considered include manufacturability, reliability, signal integrity, size, weight, power consumption, heat dissipation, etc. Conflicts among these multiple criteria are common. The design process involves many tradeoff analyses and the optimization of conflicting requirements [1,2,7,8]. While designing the package for an application, it is important to have the module defined before committing to a specific package design.

The following parameters are considered. The establishment of and adherence to good chip design rules are essential to achieving high yields in IC package assembly. The total number of terminals at packaging interfaces is a major cost factor. Signal interconnections and terminals constitute the majority of conducting elements, especially in low-cost packaging.

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Other conductors supply power and provide ground or other reference voltages. Circuit partitioning and an appropriate net topology are essential to minimize the reflection noise in the packaging of high-speed circuitry and multichip modules. The number of terminals supporting a group of circuits is strongly dependent on the function of this group.

With memory ICs, the smallest pinout can be obtained because the stream of data can be limited to a single bit. Exactly the opposite is the case with groups of logic circuits owing to a random partitioning of a computer.

Thermal Stress and Strain in Microelectronics Packaging

The pinout requirement is one of the key driving parameters for all levels of packaging [1—3,9,10]. The two primary electrical functions of an electronic package are to deliver power to the circuits and to carry electrical signals from one circuit to another. Hence, the major electrical design objectives in electronic packaging are to maintain signal fidelity in signal paths and to minimize noise generation in electrical power conductors while minimizing the cost.

High-speed systems have unique requirements for packaging technology as a result of the relatively short wavelength of the electromagnetic energy and the circuit components must be considered as distributed elements rather than as lumped elements. High-speed digital design, in contrast to digital design at low speeds, emphasizes the behavior of passive circuit elements such as wires, circuit boards, and so on.

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At higher speeds, as a signal propagates through the package, it is degraded owing to reflections and line resistance see Table 8. Controlling the resistance and the inductance. Besides, controlling the impedance environment of the signal distribution path in the package to mitigate the reflection-related noise is important. Reflections cause an increase in the transition time and may split the signal into two or more pulses with the potential of causing erroneous switching in the subsequent circuit and thus malfunctioning of the system.

Controlling the capacitive coupling between signal traces in the signal distribution path to reduce cross talk is also important [11—14]. Increased speed of the devices demands that package bandwidth be increased to reduce undue distortion of the signal.

All these criteria are related through geometric variables such as conductor cross section and length, dielectric thickness, and the dielectric constant of the packaging body. These problems are usually handled with transmission line theory [15—17].

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Reliability at all levels of packaging is directly related to operating temperature. Higher operating tem- peratures accelerate various failure mechanisms such as creep, corrosion, and electromigration. In addition, an electronics packaging is a composite structure.

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Owing to the thermal expansion mismatch of different parts of the packaging, thermal stresses and strains can occur inside a packaging system while it is being manufactured and while it is being used [18,19]. The demands to reduce packaging signal delay and increase packaging density have made chip power dissipation a major concern.

Thus, thermal temperature, stress, and strain management is vital for microelectronics packaging designs and analyses. In a simplistic heat transfer model of a packaged chip, the heat is transferred from the chip to the surface of the package by conduction and from the package surface to the ambient by convection and radiation. Figure 8. If there are parallel paths for heat flow, the thermal resistances are combined in exactly the same manner as electrical resistors in parallel. Typically, the temperature difference between the case and ambient is small, and hence radiation can be neglected.

The conductive thermal resistance is mainly a function of package materials and geometry. The temperature dependence of materials selected in design must be considered when high power is required.

The junction temperature T j depends on package geometry, package orientation in the application, and the conditions of the ambient in the operating environment. Order by , and we can deliver your NextDay items by. In your cart, save the other item s for later in order to get NextDay delivery. We moved your item s to Saved for Later.

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